Digital semiconductor circuits may employ a clock signal to help coordinate operation of flip-flops, logic gates and other elements. Typically a clock signal having a square wave may be used. Further, it is generally desirable for the clock signal to exhibit a duty cycle of 50% such that the high and low signals are generated for equal periods of time. Generally, this characteristic helps prevent metastability, sequencing errors, and other timing errors in the digital circuit.
Accordingly, clock signal generators may employ a correction loop to reduce deviations from the desired 50% duty cycle. Conventional techniques for implementing duty cycle correction loops include the use of a resistor-capacitor (RC) circuit to take the average of the high and low values of the clock signal for comparison to one-half the supply voltage. By employing a feedback circuit to drive the difference to zero, a 50% duty cycle may be achieved. Although effective, these approaches typically involve the use of large capacitance and resistance values to average the high and low signals. As a result, the RC circuit may have a relatively slow response time. Further, the techniques may be applied directly only when the duty cycle being corrected is greater than 50%. If the duty cycle is less than 50%, the clock signal is inverted before correction to result in a duty cycle greater than 50% to allow the technique to be applied. Inverting the clock signal may lead to a disruption in the operation of circuits receiving the clock signal, such as phase locked loops (PLLs) and the like.
Accordingly, what have been needed are systems and methods for correcting the duty cycle of a clock signal offering improved response times. There is also a need for techniques for duty cycle correction that reduce disruptions to operation. This disclosure satisfies these and other needs.